EnzymeCon3 Planning Survey
Hey folks, we’re in the process of planning EnzymeCon3. If you’re potentially interested in the event (or have ideas/feedback you’d like to share), please fill out this survey. docs.google.com...
View Article[RFC] UHDI: a JSON debug-info document emitted from the Debug dialect
--emit-uhdi makes firtool write one JSON document per compilation, to the path you give it. It describes the design the way the frontend saw it: source names, source types, enum variants, scopes, and,...
View Article[torch-mlir] Where should QDQ fusion live for the new quantized_decomposed...
Hi all, We are building a compiler that consumes quantized models (both PyTorch and ONNX) through torch-mlir, targeting TOSA/Linalg. Our end goal is having integer ops followed by requantization, i.e....
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[RFC] AXI4 Dialect
This RFC proposes a dialect for representing AXI4 networks, drafted by myself and @moritzs - if there’s an ODM slot available to discuss this any time soon then that would be great, and any feedback...
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[RFC] A Core-Level Probe Dialect
Previous Discussions github.com/llvm/circt [RFC] Add Probe dialect prototype for HW-level probe modeling (#10741) main ← nanjo712:feat/probe-dialect-rfc opened 05:26AM - 27 Jun 26 UTC nanjo712 +1043...
View ArticleUHDI (Unified Hardware Debug Info): structured debug-info export for...
Background HGLDD is consumed by Synopsys VCS/Verdi, so CIRCT cannot extend it freely: changes risk breaking the Synopsys side, and the format is tailored to VCS internals anyway. When surfer-tywaves...
View Article[RFC] RVCC: An LLVM Incubator for High-Performance RISC-V Compiler Optimizations
TL;DR We propose to launch RVCC (RISC-V Compiler Collaboration for High-Performance Cores) as an LLVM Incubator project. RVCC will provide an incubation and validation pipeline for optimization...
View ArticleCIRCT Project Policy on Contributions from thomasnormal/circt Fork
On behalf of the CIRCT project maintainers, this post seeks to clarify the project’s stance on contributions and AI tool use. The CIRCT project is an LLVM Incubator Project and therefore adheres to...
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Require Pull Requests for all CIRCT commits
As discussed in the ODM today, we are going to follow LLVM’s policy of requiring GitHub pull requests for all commits to the main branch. Relevant discussions: RFC: Require Pull Requests for all...
View ArticleIs there a way to externalize weights in torch-mlir output?
Hi all, I started to explore the torch_mlir utilities, and try to lower to MLIR from pytorch. As far as I can tell the only/stable way to convert pytorch models using torch_mlir is by using the fx...
View ArticleHow to lower tm_tensor.attention to linalg (linalg on tensors backends) by...
I’m working on optimizing model inference scenarios based on affine. When I used torch-mlir to descent the llama2 model along the linalg on tensor backends path, I encountered an operator called...
View ArticleFailed to legalize operation 'seq.firmem'
Hello, I am trying to run the circt-bmc tool against the example below. The example is obtained essentially from lowering a SystemVerilog description into MLIR using circt-verilog. Upon running...
View ArticleAre there any examples of using Enzyme with llvm flang (aka flang-new)?
New to enzyme and was hoping someone could point me to a good tutorial or example of a fortran project that is using enzyme. From looking at the tests in the enzyme repository it appears at least that...
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Handshake-to-hw lowering with buffers
I am trying to lower a handshake program: handshake.func @add(%a : i32, %b : i32) -> i32{ %add1 = comb.add %a, %a : i32 %add2 = comb.add %add1, %b : i32 return %add2: i32 } and in particular, since...
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CIRCT: exported verilog from mlir can't be synthesized with yosys
Given the input firrtl file, I can produce synthesizable Verilog with firtool --lowering-options=disallowLocalVariables,disallowPackedArrays foo.fir. However, when I try to first emit mlir with...
View Article[Job Ad] Cambridge PhD Position on CIRCT | Apply before Dec 3rd
Interested in doing a PhD while working on CIRCT? We have funding for five PhD positions via CASCADE and likely more via Cambridge PhD Fellowships – all aimed at working at the intersection of...
View ArticleQuery related to operations like sv.assign
Hi folks, The operations like sv.bpassign or sv.assign in the SV dialect do not have any result like shown in the following piece of CIRCT code represing a 2x1 mux: hw.module @mux_2_to_1(in %a: i1, in...
View ArticleWhy my torch-mlir can do nothing?
I installed torch-mlir by pip install, the envs are all followed by the github.md. But my torch_mlir doesn’t have any functions, could you tell me what’s wrong with my torch-mlir? Python 3.11.13...
View ArticleDC simulation
To understand the semantics of DC dialect, I am trying to simulate it at a lower level (e.g. with arcilator or verilator). To do this, I am starting from one of the examples in the handshake-to-dc...
View ArticleLowering From LTL to Core
I’m fairly new to CIRCT, so apologies if I’m overlooking something obvious. I was experimenting with the LTL dialect and tried lowering it to the core dialect using the ./circt-opt -lower-ltl-to-core...
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