How to separate the body and dialect resources from a module in torch-mlir...
Following the github example of torch-mlir, I have translated the resnet18 into mlir: resnet18 = torchvision.models.resnet18(pretrained=True) resnet18.eval() module = torchscript.compile(resnet18,...
View ArticleCustomizing Function Export with fx.export_and_import
I am trying to export the MLIR file of Llama2 using fx.export_and_import in torch_mlir. By default, it seems to export the model’s forward function. Is there a way to specify which function to export,...
View ArticleFIRRTL equivalent to Yosys's `$initstate`
I’m building a embedded HDL library in Rust that generates FIRRTL, but I’m running into a problem when I’m trying to run formal verification using SymbiYosys on the output: I can’t figure out how to...
View ArticleEvaluation mode behavior for training-specific parameters for pytorch model
Hi All, I’m not sure if this is the right forum to ask this question; if it is not, please let me know. I have the below clarification question related to pytorch module.eval(): The document below...
View ArticleJittable error of iree-turbine
I followed the iree-turbine steps to set up the environment and executed the corresponding samples in order. The first two samples, AOT MLP With Static Shapes and AOT MLP with a Dynamic Batch Size,...
View Article[Job Ad] PhD position in Munich, Germany, on CIRCT, Yosys and Verilator
Hi everyone, I have a fully funded PhD position to fill in Munich to work on interoperability of CIRCT, Yosys and Verilator, and related topics. You can find some information here: Open Source Chip...
View ArticleLLVM Dev Meeting CIRCT Meetup?
I remember there was some talk in an ODM a couple of weeks back of planning a bay area CIRCT meetup to coincide with the LLVM Dev Meeting next week. Are there any plans for this? Would be great to...
View ArticleOperation cloning in graph regions with use before def values
Hi, I’m working on building a pass to outline operations that are part of strongly connected components within an HwModuleOp into separate submodules. To achieve this, I need to clone the necessary...
View ArticleCIRCT: Lowering Upstream MLIR into Verilog
Hello, I’m a newcomer to both MLIR and CIRCT. I recently created a small dialect in MLIR and successfully lowered its operations to LLVM as a test. Now, I’m trying to lower that same dialect into...
View ArticleProper way to obtain arcilator-runtime.h for C++ integration
When using the arcilator from CIRCT its generated code requires arcilator-runtime.h for C++ compilation. However, this header is missing in the official pre-built release tarbal ( from GitHub release...
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Dealing with files emitted by addResource / HGLDD in firtool
Using a modern chisel Version like 6.7.0, calls to addResource will emit a firrtl.transforms.BlackBoxInlineAnno inside the chirrtl (or firrtl?) file. When lowered to Verilog using a fairly new...
View ArticleFirtool v1.114.1 segmentation fault with Chisel 7.0.0-RC1
Description I’m encountering a segmentation fault when invoking firtool v1.114.1 on a .fir file generated by Chisel 7.0.0-RC1. The crash reproduces consistently with the command below. Environment OS:...
View ArticleLowering From LTL to Core
I’m fairly new to CIRCT, so apologies if I’m overlooking something obvious. I was experimenting with the LTL dialect and tried lowering it to the core dialect using the ./circt-opt -lower-ltl-to-core...
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