Is there a way to get firtool to output arrays in a module interface?

Can firtool create arrays in the module interfaces from a Chisel array?

If I run verilator -cc test.v on test.v:

module array_example
(
    input [63:0] int_array [7:0], // Array of 8, 64-bit integers
    output reg [63:0] sum
);

    initial sum = 64'b0;

    always @(*) begin
        sum = 64'b0;
        for (int i = 0; i < 8; i = i + 1) begin
            sum = sum + int_array[i];
        end
    end

endmodule

I get an array in the module interface:

class Vtest VL_NOT_FINAL : public VerilatedModel {
  private:
    // Symbol table holding complete model state (owned by this class)
    Vtest__Syms* const vlSymsp;

  public:

    // PORTS
    // The application code writes and reads these signals to
    // propagate new values into/out from the Verilated model.
    VL_OUT64(&sum,63,0);
    VL_IN64((&int_array)[8],63,0);

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