Handshake FuncOp creation
Hi, everybody! I’ve come up with an idea of my custom dialect. Say, I have something like this: mydialerct.module @name inputs(...) outputs(...) { mydialect.pull %input // pull something out of the...
View ArticleLowering to FIRRTL dialect: lowering to FModuleOp from an Op that does not...
Hello. I am having trouble while lowering to FModuleOp. The problem is that my Op from which I am lowering does not have clock and reset ports. The result is that I cannot insert the body of my Op...
View ArticleFirtool creates empty .sv files when it is passed "-o=."
Any ideas on why this might be happening? I’m getting empty .sv files when firtool is passed “-o=.”, whereas it works fine if I pass in “-o=test/” $ firtool --version LLVM (http://llvm.org/): LLVM...
View ArticleFirtool - how do I remove the header?
I am generating some .sv files that I am committing to git. Therefore I would like to exclude this header, since it will change from version to version and only the changes to the .sv file are...
View ArticleTosa.reciprocal' op operand #0 must be tensor of number values, but got 'tensor'
Hello everyone. I seem to be having some problems lately and was hoping someone could give me some advice. The thing is this. I’m using torch-mlir to convert models to MLIR, but I’m finding that it...
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Error: unknown type `clock` in dialect `seq`
I’m getting this ^^^ error when I call mlirModule = parseSourceFile<ModuleOp>(sourceMgr, &context); for a module: hw.module private @Rocket(%clock: !seq.clock, ...) any suggestions would be...
View ArticleHelp debugging CIRCT - LLDB doesn't find half the names
Hello there! I’ve recently been exposed to Circt at my student assistant job and have been playing around with it, seeing what kind of stuff the IR supports. There I have run into a very curios bug...
View ArticleNew Community Meeting / Developer Hour Schedule
Hi all, It’s been really nice to see contributions to Torch-MLIR from people all over the world. In order to make attendance to our meetings easier for people, we have decided to change the developer...
View ArticleTorch MLIR PyTorch2 Uplift
At the mlir dev conference, I was chatting with our colleagues from ByteDance, and we thought it was time to get a workgroup together to land the PyTorch2 uplift that we talked about a couple of weeks...
View ArticleTEST 'CIRCT :: firtool/firtool.fir' FAILED
Hello, after succeed building circt with ninja, I executed ninja check-circt in main branch and failed. The newest commit I use is 12d168 I run it on Ubuntu 22.04, clang: 17.0.0. [0/1] Running the...
View ArticleWhat's the semantics of "hw.generator.schema", "hw.module.extern", and...
circt.llvm.org 'hw' Dialect - CIRCT Circuit IR Compilers and Tools I encountered some challenges while reading this documentation, specifically regarding the semantics of “hw.generator.schema,”...
View ArticleDoes torch-mlir support the FFT function in the torch library?
As the title.There is an error when I tried to use torch.fft.fft. 2 posts - 2 participants Read full topic
View ArticleError when performing complex number addition
I’m sorry, I have quite a few questions. There is an error when I try to run the following code: import torch import torch_mlir class FFT(torch.nn.Module): def forward(self, z1, z2): temp=z1+z2 return...
View ArticleIs there a way to get firtool to output arrays in a module interface?
Can firtool create arrays in the module interfaces from a Chisel array? If I run verilator -cc test.v on test.v: module array_example ( input [63:0] int_array [7:0], // Array of 8, 64-bit integers...
View ArticleHW dialect support for parameterizable module
Hi everybody! I’m currentling trying to express the parameter semantics using hw dialect when defining a module in SystemVerilog like this: module foo #( bitwidth = 32 ) ( input [bitwidth-1:0] i,...
View ArticleEnzymeCon 2 Planning
Hi all, We’re presently in the process of planning the second Enzyme annual meeting. All is subject to change, but I wanted to reach out to see if folks here have strong opinions either way. We’re...
View ArticleIssue with PyTorch to MLIR Compilation using torch-mlir: Missing Input...
Hello everyone, I hope you’re doing well. I’ve encountered a problem while working with torch-mlir to emit MLIR from a PyTorch model. When using the torch_mlir.compile method, one of the inputs...
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Firtool verilog instead of systemverilog
I want to build rocket chip rtl. I modified the build.sc of rocke chip hope the firtool would generate verilog instead of systemverilog, but it failed. What should I do to generate verilog instead of...
View ArticleSupport for Bazel Build System
Hi everyone, I am new to the LLVM/MLIR ecosystem. Are there any plans to add Bazel build support to CIRCT? I am currently working on a project that uses Bazel to manage my LLVM and MLIR dependencies,...
View ArticleRead from modport
Hi there, I have a question regarding how to read from an modport that is defined in a module definition. For example, when declaring a hw.module like this: module { sv.interface @interface_def{...
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