Lowering to FIRRTL dialect: lowering to FModuleOp from an Op that does not have clock and reset ports

Hello. I am having trouble while lowering to FModuleOp. The problem is that my Op from which I am lowering does not have clock and reset ports. The result is that I cannot insert the body of my Op into FModuleOp because of the different number of block arguments. I am doing it like this:

 auto &region = graphOp->getRegions().front();
 rewriter.mergeBlocks(&region.getBlocks().front(),
     fModuleOp.getBodyBlock(), fModuleOp.getBodyBlock()->getArguments());

Is there a way to insert a body of my Op into a FModuleOp without adding clock and reset ports to my Op?

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